Zen 6 AMD EPYC Venice CPU breaks cover as its CCD poses for a photoshoot next to TSMC and AMD’s CEOs

Zen 6 AMD EPYC Venice CPU breaks cover as its CCD poses for a photoshoot next to TSMC and AMD’s CEOs

  • AMD shows off its first 2nm-class Venice CPU die built using TSMC’s N2 node
  • Venice, built on Zen 6, targets high-performance computing workloads
  • AMD and TSMC hope to deepen their collaboration for future innovations

AMD has announced it has successfully produced the first 2nm-class silicon for its next-generation EPYC processor, codenamed “Venice” which is expected to launch in 2026 as part of AMD’s 6th Generation EPYC lineup.

The core complex die (CCD) is the first high-performance computing product to be taped out and brought up using TSMC’s advanced N2 process technology.



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